1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having self-refresh and back-bias circuitry.
2. Description of the Related Art
A self-refresh operation is performed to protect data stored in memory cells of a semiconductor memory device such as a DRAM (dynamic RAM). The self-refresh operation regenerates stored information in all memory cells during a given period using a refresh timer.
During the self-refresh operation, a normal read-write operation is interupted. The power consumed during the self-refresh operation is mainly due to a self-refresh current, a back-bias current and a current consumed by a back-bias generator.
The back-bias generator detects a substrate voltage level (also known as back-bias voltage). An oscillator and charge pump circuit provided therein are controlled in response to the detected substrate voltage. The operation and structure of a conventional back-bias generator are disclosed in U.S. Pat. No. 4,471,290.
The self-refresh operation regenerates information in memory cells during a given period under the control of a refresh timer and an address counter coupled thereto. During this period, write circuits associated with peripheral circuits of a memory array are disabled. The address counter is coupled to an address buffer so as to continue a write operation when the refresh operation is completed. Conventional self-refresh circuitry is disclosed in U.S. Pat. Nos. 4,809,233, 4,829,484 and 4,939,695.
The self-refresh operation and the back-bias operation are provided for preserving data in memory cells. The back-bias operation maintains an electric potential of a substrate at a predetermined level. The self-refresh operation occurs during a self-refresh period to protect the data stored in memory cells. The back-bias generator must be inactive during the self-refresh operation. If not deactivated, the back-bias generator consumes power unnecessarily during this period. A semiconductor memory device having both these functions is disclosed in an article published by ISSCC of IEEE, pp 230-231, entitled "A 38ns 4 Mb DRAM with a Battery Back-up (BBU) Mode" (February 1990).
FIG. 1A shows a configuration of a semiconductor memory device disclosed in the above article. The 4Mbit DRAM includes a batery-backup (BBU) mode. The BBU mode is a kind of self-refresh mode, however, its power dissipation is reduced compared to that of a normal refresh operation. More specifically, BBU is an operation mode during which the data retention operation is performed in a VLSI semiconductor memory device having low power consumption as used in a portable computer, such as lap-top or note-book personal computers which are powered by a battery.
FIG. 1B shows a timing diagram for the BBU mode for the circuit in FIG. 1A. The DRAM enters the BBU mode when the CAS is held low for more than 16 ms after a CBR (CAS before RAS) sequence, without a refresh cycle. The BBU mode continues as long as the CAS is low, and the DRAM is reset to the normal mode on rising RAS.
The refresh timer, consisting of a ring oscillator and binary counters, generates a refresh request signal with a 64 .mu.s period. As a result, all memory cells are refreshed within 4096 cycles per 256 ms during a BBU mode. This refresh period is 16 times longer than than of prior self-refresh circuits used in similar 4Mbit DRAMs.
FIG. 2 shows a circuit diagram of the back-bias (Vbb) generator and BBU control circuit interconnection of FIG. 1A. The duty cycle of this circuit is one eighth that in the normal operation since the substrate current during BBU mode is lower than in normal mode. This back-bias generator works during reset and sensing operations as determined by the refresh request signal output from the BBU control circuit.
When the refresh timer supplies a signal having a period of 16 ms to the BBU control circuit, the BBU control circuit generates a BBU enable signal. After the BBU enable signal is generated, the refresh timer generates a clock pulse of 64 .mu.s period, and the BBU control circuit generates a refresh request signal in response to the 64 .mu.s clock pulse. Based on the refresh request signal, the refresh operation is performed by operating one array driver each 64 .mu.s period.
With reference to FIG. 2, the refresh request signal from the BBU control circuit controls the operation of an oscillator used in connection with the back-bias generator. While the refresh request signal is at logic "low" state, i.e., while the refresh operation is performed, the logic "low" state refresh request signal disables a NAND gate of the oscillator so as to inactivate the back-bias generator.
As described, the back-bias generator is active while the refresh request signal is enabled and is inactive while the self-refresh operation is performed. As shown in prior art FIGS. 1A, 1B and 2, the refresh request signal is generated by the refresh timer so as to provide a constant period (or constant frequency).
The refresh period, which is selected to be 64 .mu.s in the above embodiment, is chosen using a predetermined number of binary counters as shown in FIG. 1. When it becomes necessary for a user to vary the refresh period to optimize power consumption in a particular system, changing the number of binary counters may be a great inconvenience.